Conventionally, there have been known analog-to-digital conversion circuits (hereinafter referred to as “ADCs (Analog Digital Converters)”), which convert an analog signal to a digital signal. Hereinafter, the term “AD conversion” will be used to refer to an operation for converting an analog signal to a digital signal. One known example of such ADCs is an ADC including a comparator configured to output a comparison result signal by comparing an analog signal and a ramp signal having a potential varying depending on time, a counter configured to output a count signal by counting a clock pulse signal, and a memory to which the comparison result signal and the count signal are input. In this type of ADC, the memory holds the count signal, which is a digital signal, according to the comparison result signal, whereby the analog signal is converted into a digital signal.
Japanese Patent Application Laid-Open No. 2008-187420 discusses a technique for performing an AD conversion while changing the potential of a ramp signal depending on time. FIG. 14 illustrates the configuration of a ramp signal output circuit configured to generate the ramp signal discussed in Japanese Patent Application Laid-Open No. 2008-187420. FIG. 14 accompanying the present application corresponds to FIG. 19 of Japanese Patent Application Laid-Open No. 2008-187420, although the illustrated components are relabeled in FIG. 14. The ramp signal output circuit discussed in Japanese Patent Application Laid-Open No. 2008-187420 charges and discharges an integral capacitance 51, thereby shifting the potential of the ramp signal from a potential of the auto-zero level to a predetermined potential that starts to vary depending on time.
In the ADC discussed in Japanese Patent Application Laid-Open No. 2008-187420, a current is applied to the integral capacitance 51 disposed between input and output terminals of an integrating amplifier 50 to charge and discharge the integral capacitance 51 to shift the potential of the ramp signal to the predetermined potential that starts to vary depending on time. Therefore, this ADC requires some time for charging and discharging the integral capacitance 51 to shift the potential of the ramp signal from a certain potential to the predetermined potential that starts to vary depending on time.